Flip-flop D


A D flip-flop is a flip-flop that has one D data input and one clock input (CLK). This flip-flop is often called a delay flip-flop because the data at input D, either 0 or 1, is delayed for 1 clock pulse from input to output Q.

Figure 1 D . flip-flop logic symbol

The D flip-flop can be formed from a ticking R-S flip-flop by adding an inverter as shown in the figure below:
Figure 2 D . Flip-flop Circuit

Figure 3 Commercial D flip-flop

The truth table of the D 7474 . flip-flop

From the table above, the PS (Preset) input sets the Q output to 1 when opened by a logic 0. The CLR (Clear) input sets the Q output to 0 when it is opened by a logic 0. The PS and CLR inputs will reject the D and CLK inputs. Remember that PS and CLR are not clock dependent, only D is clock dependent. If there is data being stored in D, then logic 0 is given to the PS or CLR, then the flip-flop will execute the PS and CLR instructions regardless of the clock pulse.
The D flip-flop can be set and reset using the D and CLK inputs. The last two rows of the truth table use one clock pulse to transfer data from input D to output Q of the flip-flop.
The D flip-flops are coupled to each other to form a shift register and a storage register. Recall that the D flip-flop delays data to reach output Q of one clock pulse and is called a delay flip-flop.

Figure 4 Pulse sequence problem on the D . flip-flop
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